-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "04/06/2021 21:37:08"

-- 
-- Device: Altera EP3C40F780C8 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	zl_2346_pre1 IS
    PORT (
	D0 : OUT std_logic;
	A : IN std_logic;
	B : IN std_logic;
	C : IN std_logic;
	q : IN std_logic;
	D1 : OUT std_logic;
	D2 : OUT std_logic;
	D3 : OUT std_logic;
	D4 : OUT std_logic;
	D5 : OUT std_logic;
	D6 : OUT std_logic;
	D7 : OUT std_logic
	);
END zl_2346_pre1;

-- Design Ports Information
-- D0	=>  Location: PIN_AF2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D1	=>  Location: PIN_AE2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D2	=>  Location: PIN_AD2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D3	=>  Location: PIN_AA3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D4	=>  Location: PIN_AC7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D5	=>  Location: PIN_AE1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D6	=>  Location: PIN_AE3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D7	=>  Location: PIN_AB3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- C	=>  Location: PIN_V8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- A	=>  Location: PIN_AB7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- B	=>  Location: PIN_AA5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- q	=>  Location: PIN_AA4,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF zl_2346_pre1 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_D0 : std_logic;
SIGNAL ww_A : std_logic;
SIGNAL ww_B : std_logic;
SIGNAL ww_C : std_logic;
SIGNAL ww_q : std_logic;
SIGNAL ww_D1 : std_logic;
SIGNAL ww_D2 : std_logic;
SIGNAL ww_D3 : std_logic;
SIGNAL ww_D4 : std_logic;
SIGNAL ww_D5 : std_logic;
SIGNAL ww_D6 : std_logic;
SIGNAL ww_D7 : std_logic;
SIGNAL \D0~output_o\ : std_logic;
SIGNAL \D1~output_o\ : std_logic;
SIGNAL \D2~output_o\ : std_logic;
SIGNAL \D3~output_o\ : std_logic;
SIGNAL \D4~output_o\ : std_logic;
SIGNAL \D5~output_o\ : std_logic;
SIGNAL \D6~output_o\ : std_logic;
SIGNAL \D7~output_o\ : std_logic;
SIGNAL \B~input_o\ : std_logic;
SIGNAL \C~input_o\ : std_logic;
SIGNAL \q~input_o\ : std_logic;
SIGNAL \A~input_o\ : std_logic;
SIGNAL \inst23~combout\ : std_logic;
SIGNAL \inst24~combout\ : std_logic;
SIGNAL \inst25~combout\ : std_logic;
SIGNAL \inst26~combout\ : std_logic;
SIGNAL \inst27~combout\ : std_logic;
SIGNAL \inst28~combout\ : std_logic;
SIGNAL \inst29~combout\ : std_logic;
SIGNAL \inst30~combout\ : std_logic;

BEGIN

D0 <= ww_D0;
ww_A <= A;
ww_B <= B;
ww_C <= C;
ww_q <= q;
D1 <= ww_D1;
D2 <= ww_D2;
D3 <= ww_D3;
D4 <= ww_D4;
D5 <= ww_D5;
D6 <= ww_D6;
D7 <= ww_D7;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

-- Location: IOOBUF_X0_Y6_N2
\D0~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst23~combout\,
	devoe => ww_devoe,
	o => \D0~output_o\);

-- Location: IOOBUF_X0_Y7_N16
\D1~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst24~combout\,
	devoe => ww_devoe,
	o => \D1~output_o\);

-- Location: IOOBUF_X0_Y9_N9
\D2~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst25~combout\,
	devoe => ww_devoe,
	o => \D2~output_o\);

-- Location: IOOBUF_X0_Y6_N23
\D3~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst26~combout\,
	devoe => ww_devoe,
	o => \D3~output_o\);

-- Location: IOOBUF_X0_Y8_N23
\D4~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst27~combout\,
	devoe => ww_devoe,
	o => \D4~output_o\);

-- Location: IOOBUF_X0_Y7_N9
\D5~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst28~combout\,
	devoe => ww_devoe,
	o => \D5~output_o\);

-- Location: IOOBUF_X0_Y4_N16
\D6~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst29~combout\,
	devoe => ww_devoe,
	o => \D6~output_o\);

-- Location: IOOBUF_X0_Y9_N23
\D7~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst30~combout\,
	devoe => ww_devoe,
	o => \D7~output_o\);

-- Location: IOIBUF_X0_Y7_N22
\B~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_B,
	o => \B~input_o\);

-- Location: IOIBUF_X0_Y7_N1
\C~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_C,
	o => \C~input_o\);

-- Location: IOIBUF_X0_Y8_N1
\q~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_q,
	o => \q~input_o\);

-- Location: IOIBUF_X0_Y8_N15
\A~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_A,
	o => \A~input_o\);

-- Location: LCCOMB_X1_Y8_N24
inst23 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst23~combout\ = ((!\B~input_o\ & (!\C~input_o\ & !\A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100011111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst23~combout\);

-- Location: LCCOMB_X1_Y8_N10
inst24 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst24~combout\ = ((!\B~input_o\ & (\C~input_o\ & !\A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111101001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst24~combout\);

-- Location: LCCOMB_X1_Y8_N4
inst25 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst25~combout\ = ((\B~input_o\ & (!\C~input_o\ & !\A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100101111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst25~combout\);

-- Location: LCCOMB_X1_Y8_N22
inst26 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst26~combout\ = ((\B~input_o\ & (\C~input_o\ & !\A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111110001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst26~combout\);

-- Location: LCCOMB_X1_Y8_N8
inst27 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst27~combout\ = ((!\B~input_o\ & (!\C~input_o\ & \A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst27~combout\);

-- Location: LCCOMB_X1_Y8_N18
inst28 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst28~combout\ = ((!\B~input_o\ & (\C~input_o\ & \A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst28~combout\);

-- Location: LCCOMB_X1_Y8_N20
inst29 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst29~combout\ = ((\B~input_o\ & (!\C~input_o\ & \A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst29~combout\);

-- Location: LCCOMB_X1_Y8_N30
inst30 : cycloneiii_lcell_comb
-- Equation(s):
-- \inst30~combout\ = ((\B~input_o\ & (\C~input_o\ & \A~input_o\))) # (!\q~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \B~input_o\,
	datab => \C~input_o\,
	datac => \q~input_o\,
	datad => \A~input_o\,
	combout => \inst30~combout\);

ww_D0 <= \D0~output_o\;

ww_D1 <= \D1~output_o\;

ww_D2 <= \D2~output_o\;

ww_D3 <= \D3~output_o\;

ww_D4 <= \D4~output_o\;

ww_D5 <= \D5~output_o\;

ww_D6 <= \D6~output_o\;

ww_D7 <= \D7~output_o\;
END structure;


